1. Field of the Invention
The present invention relates to a technique capable of precisely performing a test with a high reproducibility on a certain pattern of a 64B/66B encoder or decoder of a 10 GBASE-R PCS (physical coding sublayer), defined in IEEE802.3, in various types of transmission apparatuses or communication apparatuses having a 10-Gigabit Ethernet (registered trademark) interface, in which B of the 64B/66B represents a bit.
2. Discussion of Related Art
The basic flow of a 64B/66B encoding sequence of a 10 GBASE-R PCS is RX-INT (initial state)→RX-C (control code process state)→RX-D (data process state)→RX-T (termination code state) as described in a non patent literature “IEEE802.3 Receive State Machine”. However, in order to test a decoding sequence at a receiver side, for example, when an attempt is made to test the case in which a termination code is input to the RX-C state, the RX-C is transited to RX-E (error code process state) in a typical encoding process, and thus it is impossible to perform the test in the encoding process of data from a higher layer.
In the case where an abnormal state occurs as mentioned above, the test is performed by causing a loss of data in a physical layer such as turning on/off of an optical output and inserting an error into the physical layer.
However, the above-described method has a problem that an accurate test cannot be performed since it has a low reproducibility and an intended operation is not performed due to initialization of the apparatus.